There is a request to incorporate some kind of security function such as device identification in a semiconductor device such as LSI, for discriminating an imitation (copy) product of the device. In that case, a circuit having the security function is normally formed in a so-called front end of line (FEOL) where elements such as an FET are formed on a semiconductor wafer. In conjunction with the miniaturization of wiring pitch typified by a recent wiring width of ten-odd nm, the design of semiconductor device and the fablessness of manufacturers, the elements (circuits) in the FEOL have been increasingly formed by specific external contract semiconductor manufacturers (specialized IC foundries) equipped with a semiconductor manufacturing process adapted to the miniaturization.
However, in that case, design information of the circuit having the security function flows out to the external contract semiconductor manufacturer, and the security function may be known to a third party including device imitators due to information leakage escaping through the non-disclosure agreement and the like. Moreover, the position of the circuit having the security function provided in the FEOL is easily identified, and its content is also likely to be easily analyzed.
On the other hand, in a back end of line (BEOL) formed above the FEOL, only a plurality of stacked wiring layers are usually provided, and the wiring pitch becomes wider toward an upper layer in order to enable connection with external terminals, and thus the above-described miniaturization process required in the FEOL is not needed in the BEOL. Note that, normally, some kind of function circuit other than the wiring layers is hardly provided in the BEOL.
International Publication WO2011/044385 discloses a chip identifier structure including at least two through silicon vias each wired to an external electrical connection, and a vertically stackable die (chip) having a chip identification decoding logic coupled to the chip identifier structure.
Chang-Hong Shen, et al. “Monolithic 3D Chip Integrated with 500 ns NVM, 3 ps Logic Circuits and SRAM” (9.3.1-9.3.4, Electron Devices Meeting (IEDM), 2013 IEEE International, 9-11 Dec. 2013) discloses a thin MOSFET formed in a back end of a three-dimensional stacked IC structure.